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asahi kasei [ak4370] ms0595-e-00 2007/03 - 1 - general description the ak4370 is a 24-bit dac with headphone amplifier. the ak4370 features an analog mixing circuit that allows easy interfacing in mobile phone and por table communication desi gns. the integrated headphone amplifier features ?pop-noise free? power-on/off, a mu te control, and it delivers 40mw of power into 16 . the ak4370 is packaged in a 24-pin qfn (4mm4mm) package, ideal for portable applications. feature ? multi-bit ? dac ? sampling rate - 8khz 48khz ? on chip perfect filtering 8 times fir interpolator - passband: 20khz - passband ripple: 0.02db - stopband attenuation: 54db ? digital de-emphasis filter: 32khz, 44.1khz and 48khz ? system clock - 256fs/384fs/512fs/768fs/1024fs - input level: ac couple input available ? audio i/f format: msb first, 2?s complement - i 2 s, 24bit msb justified, 24bit/20bit/16bit lsb justified - master/slave mode ? digital mixing: lr, ll, rr, (l+r)/2 ? bass boost function ? digital att ? analog mixing circuit: 4 inputs (si ngle-ended or full-differential) ? stereo lineout - s/n: 90db@3.3v - output volume: +6 to ?24db (or 0 to ?30db), 2db step ? headphone amplifier - output power: 40mw x 2ch @16 , 3.3v - s/n: 92db@3.3v - pop noise free at power-on/off and mute - output volume: 0 ~ ?63db & +12/+6/0 db gain 1.5db step (0 ~ ?30db), 3db step (?30 ~ ?63db) ? p interface: 3-wire/i 2 c ? power supply: 1.6v 3.6v ? power supply current: 3.8ma @1.8v (6.8mw, dac+hp, no output) ? ta: ? 30 85 c ? small package: 24pin qfn (4mm x 4mm, 0.5mm pitch) ? register compatible with ak4368 ak4370 24-bit 2ch dac with hp-amp & output mixer
asahi kasei [ak4370] ms0595-e-00 2007/03 - 2 - block diagram audio interface hdp amp serial i/f hpl hpr lout lin2 sdata lrck cad0/csn bick scl/cclk sda/cdti mutet vcom dac dac (lch) (rch) vcom mcki digital volume bass boost de- emphasis digital filter mute pdn rout dvdd avdd hdp amp mute i2c hvdd rin2 clock divider rin1/in+ lin1/in ? vss1 vss2 figure 1. block diagram
asahi kasei [ak4370] ms0595-e-00 2007/03 - 3 - ordering information ak4370vn ? 30 +85 c 24pin qfn (0.5mm pitch) AKD4370 evaluation board for ak4370 pin layout hpr hpl rin2 lin2 rin1/in+ lin1/in ? vss1 hvdd a vdd vcom rout lout sdata bick lrck mcki dvdd vss2 mutet i2c pdn csn/cad0 cclk/scl cdti/sda ak4370vn top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 3 4 5 6
asahi kasei [ak4370] ms0595-e-00 2007/03 - 4 - comparison with ak4368 1 function function ak4368 ak4370 analog mixing 1-stereo + 1-mono single-ended input 2-stereo single-ended input or full-differential input mcki at ext mode 256fs/512fs/1024fs, 12.288mhz(max) 256fs/384fs/512fs/768fs/1024fs, 24.576mhz(max) hp-amp output volume no 0 to ?63db & +12/+6/0db 1.5db step (0 to ?30db) 3db step (?30 to ?63db) hp-amp hi-z setting no yes pll yes no 3d enhancement yes no alc yes no package 41bga (4mm x 4mm) 24qfn (4mm x 4mm) 2 register (difference from ak4368) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 0 pmpll pmlo muten pmhpr pmhpl pmdac pmvcm 01h clock control 0 fs3 fs2 fs1 fs0 pll 3 pll 2 pll 1 pll 0 02h clock control 1 0 0 m/s mckac bf ps0 ps1 mcko 03h mode control 0 0 mono1 mono0 bckp lrp dif2 dif1 dif0 04h mode control 1 ats dattc lmute smute bst1 bst0 dem1 dem0 05h dac lch att attl7 attl6 attl5 attl4 a ttl3 attl2 attl1 attl0 06h dac rch att attr7 attr6 attr5 attr4 a ttr3 attr2 attr1 attr0 07h headphone out select 0 hpg1 hpg0 lin2hr lin2hl rin1hr lin1hl darhr dalhl 08h lineout select 0 0 log lin2r lin2l rin1r lin1l darr dall 09h lineout att 0 0 0 0 atts3 atts2 atts1 atts0 0ah reserved ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 0bh reserved 0 0 alc rotm1 rotm0 lmat1 lmat0 ratt 0ch reserved 0 0 0 0 dp1 dp0 3d1 3d0 0dh headphone out select 1 0 0 0 0 rin2hr rin2hl lin1hr rin1hl 0eh headphone att 0 hpz hmute atth4 atth3 atth2 atth1 atth0 0fh lineout select 1 0 0 0 0 rin2r rin2l lin1r rin1l 10h mono mixing 0 0 0 0 l2m l2hm l1m l1hm 11h differential select 0 0 0 0 0 0 ldifh ldif 12h reserved 0 0 0 0 0 0 0 0 13h reserved 0 0 0 1 0 0 0 0 these bits are added in the ak4370 these bits are deleted in the ak4370
asahi kasei [ak4370] ms0595-e-00 2007/03 - 5 - pin/function no. pin name i/o function 1 sdata i audio serial data input pin 2 bick i/o audio serial data clock pin 3 lrck i/o input / output channel clock pin 4 mcki i external master clock input pin 5 dvdd - digital power supply pin, 1.6 3.6v 6 vss2 - ground 2 pin. connected to vss1. sda i/o control data input/output pin (i2c mode : i2c pin = ?h?) 7 cdti i control data input pin (3-wire serial mode : i2c pin = ?l?) scl i control data clock pin (i2c mode : i2c pin = ?h?) 8 cclk i control data clock pin (3-wire serial mode : i2c pin = ?l?) cad0 i chip address 0 select pin (i2c mode : i2c pin = ?h?) 9 csn i chip select pin (3-wire serial mode : i2c pin = ?l?) 10 pdn i power-down & reset when ?l?, the ak4370 is in power-down mode and is held in reset. the ak4370 should always be reset upon power-up. 11 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial 12 mutet o mute time constant control pin connected to vss1 pin with a capacitor for mute time constant. 13 lout o lch stereo line output pin 14 rout o rch stereo line output pin 15 vcom o common voltage output pin normally connected to vss1 pin with a 2.2 f electrolytic capacitor. 16 avdd - analog power supply pin, 1.6 3.6v 17 hvdd - power supply pin for headphone amp, 1.6 3.6v 18 vss1 - ground 1 pin 19 hpr o rch headphone amp output 20 hpl o lch headphone amp output 21 rin2 i rch analog input 2 pin 22 lin2 i lch analog input 2 pin rin1 i rch analog input 1 pin (ldif bit =?0? : single-ended input) 23 in+ i positive line input pin (ldif bit =?1? : full-differential input) lin1 i rch analog input 1 pin (ldif bit =?0? : single-ended input) 24 in ? i negative line input pin (ldif bit =?1? : full-differential input) note 1. all digital input pins (i2c, sda/cdti, scl/cclk, cad0/csn, sdata, lrck, bick, mcki, pdn) must not be left floating. mcki pin can be left floating only when pdn pin = ?l?.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 6 - handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog lout, rout, mutet, hpl, hpr, lin2, rin2, rin1/in+, lin1/in ? these pins should be open. digital mcki this pin should be connected to vss2. absoluate maximum rating (vss1, vss2=0v; note 2, note 3) parameter symbol min max units power supplies analog avdd 0.3 4.6 v digital dvdd 0.3 4.6 v hp-amp hvdd 0.3 4.6 v input current (any pins except for supplies) iin - r 10 ma analog input voltage ( note 4) vina 0.3 (avdd+0.3) or 4.6 v digital input voltage ( note 5) vind 0.3 (dvdd+0.3) or 4.6 v ambient temperature ta 30 85 q c storage temperature tstg 65 150 q c note 2. all voltages with respect to ground. note 3. vss1 and vss2 must be connected to the same analog ground plane. note 4. lin1/in ? , rin1/in+, lin2 and rin2 pins. max is smaller value between (avdd+0.3)v and 4.6v. note 5. sda/cdti, scl/cclk, cad0/csn, sdata, lrck, bick, mcki, pdn and i2c pins. max is smaller value between (dvdd+0.3)v and 4.6v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommend operating conditions (vss1, vss2=0v; note 2) parameter symbol min typ max units power supplies analog avdd 1.6 2.4 3.6 v ( note 6) digital ( note 7) dvdd 1.6 2.4 (avdd+0.2) or 3.6 v hp-amp hvdd 1.6 2.4 3.6 v difference avdd hvdd 0.3 0 +0.3 v note 2. all voltages with respect to ground. note 6. when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. when the ak4370 is powered-down, dvdd should be powered-down at the same time or later than avdd. when avdd and hvdd are supplied separately, avdd should be powered-up at the same time or earlier than hvdd. when the ak4370 is powered-down, avdd should be powered-down at the same time or later than hvdd. note 7. max is smaller value between (avdd+0.2)v and 3.6v. * akm assumes no responsibility for usage be yond the conditions in this datasheet.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 7 - analog characteristics (ta=25 c; avdd=dvdd=hvdd=2.4v, vss1=vss2=0v; fs=44.1khz; boost off; sl ave mode; signal frequency =1khz; measurement band width=20hz 20khz; headphone-amp: load impedance is a serial connection with r l =16 and c l =220 f. (refer to figure 38; unless otherwise specified) parameter min typ max units dac resolution - - 24 bit headphone-amp: (hpl/hpr pins) ( note 8) analog output characteristics thd+n ? 3dbfs output, 2.4v, po=10mw@16 - ? 50 ? 40 db 0dbfs output, 3.3v, po=40mw@16 - ? 20 - db ? 60dbfs output, a-weighted, 2.4v 82 90 - db d-range ? 60dbfs output, a-weighted, 3.3v - 92 - db a-weighted, 2.4v 82 90 - db s/n a-weighted, 3.3v - 92 - db interchannel isolation 60 80 - db dc accuracy interchannel gain mismatch - 0.3 0.8 db gain drift - 200 - ppm/ c load resistance ( note 9) 16 - - load capacitance - - 300 pf ? 3dbfs output ( note 10) 1.04 1.16 1.28 vpp output voltage 0dbfs output, 3.3v, po=40mw@16 - 0.8 - vrms output volume: (hpl/hpr pins) step size 0 ?30db 0.1 1.5 2.9 db (hpg1-0 bits = ?00?) ?30 ?63db 0.1 3 5.9 db gain control range max (att4-0 bits = ?00h?) - 0 - db (hpg1-0 bits = ?00?) min (att4-0 bits = ?1fh?) - ? 63 - db stereo line output: (lout/rout pins, r l =10k ) ( note 11) analog output characteristics: thd+n (0dbfs output) - ? 60 ? 50 db s/n a-weighted, 2.4v 80 87 - db a-weighted, 3.3v - 90 - db dc accuracy gain drift - 200 - ppm/ c load resistance ( note 9) 10 - - k load capacitance - - 25 pf output voltage (0dbfs output) ( note 12) 1.32 1.47 1.61 vpp output volume: (lout/rout pins) step size 1 2 3 db gain control range max (atts3-0 bits = ?fh?) - 0 - db (log1-0 bit = ?0?) min (atts3-0 bits = ?0h?) - ? 30 - db note 8. dalhl=darhr bits = ?1? lin1hl=rin1hl=lin2hl=rin2hl=lin1hr=r in1hr=lin2hr=rin2hr bits = ?0?. note 9. ac load. note 10. output voltage is proportional to avdd voltage. vout = 0.48 x avdd(typ)@ ? 3dbfs. note 11. dall=darr bits = ?1? lin1l=rin1l=lin2l=rin2l=lin1r= rin1r=lin2r=rin2r bits = ?0? note 12. output voltage is proportional to avdd voltage. vout = 0.61 x avdd(typ)@0dbfs.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 8 - parameter min typ max units linein: (lin1/rin1/lin2/rin2 pins) analog input characteristics input resistance (refer to figure 21, figure 22) lin1 pin lin1hl=lin1hr=lin1l=lin1r bits = ?1? 14 25 - k lin1hl bit = ?1?, lin1hr=lin1l=lin1r bits = ?0? - 100 - k lin1hr bit = ?1?, lin1hl=lin1l=lin1r bits = ?0? - 100 - k lin1l bit = ?1?, lin1hl=lin1hr=lin1r bits = ?0? - 100 - k lin1r bit = ?1?, lin1hl=lin1hr=lin1l bits = ?0? - 100 - k rin1 pin rin1hl=rin1hr=rin1l=rin1r bits = ?1? 14 25 - k rin1hl bit = ?1?, rin1hr=rin1l=rin1r bits = ?0? - 100 - k rin1hr bit = ?1?, rin1hl=rin1l=rin1r bits = ?0? - 100 - k rin1l bit = ?1?, rin1hl=rin1hr=rin1r bits = ?0? - 100 - k rin1r bit = ?1?, rin1hl=rin1hr=rin1l bits = ?0? - 100 - k lin2 pin lin2hl=lin2hr=lin2l=lin2r= bits = ?1? 14 25 - k lin2hl bit = ?1?, lin2hr=lin2l=lin2r bits = ?0? - 100 - k lin2hr bit = ?1?, lin2hl=lin2l=lin2r bits = ?0? - 100 - k lin2l bit = ?1?, lin2hl=lin2hr=lin2r bits = ?0? - 100 - k lin2r bit = ?1?, lin2hl=lin2hr=lin2l bits = ?0? - 100 - k rin2 pin rin2hl=rin2hr=rin2l=rin2r bits = ?1? 14 25 - k rin2hl bit = ?1?, rin2hr=rin2l=rin2r bits = ?0? - 100 - k rin2hr bit = ?1?, rin2hl=rin2l=rin2r bits = ?0? - 100 - k rin2l bit = ?1?, rin2hl=rin2hr=rin2r bits = ?0? - 100 - k rin2r bit = ?1?, rin2hl=rin2hr=rin2l bits = ?0? - 100 - k gain lin1/lin2/rin1/rin2 ? lout/rout ? 1 0 +1 db lin1/lin2/rin1/rin2 ? hpl/hpr ? 0.05 +0.95 +1.95 db power supplies power supply current normal operation (pdn pin = ?h?) ( note 13) avdd+dvdd - 3.8 5.5 ma hvdd - 1.2 2.5 ma power-down mode (pdn pin = ?l?) ( note 14) - 1 100 a note 13. pmdac=pmhpl=pmhpr=pmlo bits = ?1?, muten bit = ?1?, hp-amp no output. pmdac=pmhpl=pmhpr= ?1?, pmlo bit= ?0?, avdd+dvdd+hvdd=4.0ma (typ) @2.4v, 3.8ma (typ) @1.8v. note 14. all digital input pins are fixed to vss2.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 9 - filter characteristics (ta=25 c; avdd, dvdd, hvdd=1.6 3.6v; fs=44.1khz; de-emphasis = ?off?) parameter symbol min typ max units dac digital filter: ( note 15) passband ( note 16) ? 0.05db pb 0 - 20.0 khz ? 6.0db - 22.05 - khz stopband ( note 16) sb 24.1 - - khz passband ripple pr - - 0.02 db stopband attenuation sa 54 - - db group delay ( note 17) gd - 22 - 1/fs group delay distortion gd - 0 - s dac digital filter + analog filter: ( note 15, note 18) frequency response 0 20.0khz fr - 0.5 - db analog filter: ( note 19) frequency response 0 20.0khz fr - 1.0 - db boost filter: ( note 18, note 20) 20hz fr - 5.76 - db 100hz - 2.92 - db min 1khz - 0.02 - db 20hz fr - 10.80 - db 100hz - 6.84 - db mid 1khz - 0.13 - db 20hz fr - 16.06 - db 100hz - 10.54 - db frequency response max 1khz - 0.37 - db note 15. boost off (bst1-0 bit = ?00?) note 16. the passband and stopband frequencies scale with fs (system sampling rate). for example, pb=0.4535fs(@ ? 0.05db). sb=0.546fs(@ ? 54db). note 17. this time is from setting the 24-bit data of both channels from the input register to the output of analog signal. note 18. dac ? hpl, hpr, lout, rout note 19. lin1/lin2/rin1/rin2 ? hpl/hpr/lout/rout note 20. these frequency responses scale with fs. if high- level signal is input, the output clips at low frequency. boost filter (fs=44.1khz) -5 0 5 10 15 20 10 100 1000 10000 frequency [hz] gain [db] max mid min figure 2. boost frequency (fs=44.1khz)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 10 - dc characteristics (ta=25 c; avdd, dvdd, hvdd=1.6 3.6v) parameter symbol min typ max units high-level input voltage 2.2v dvdd 3.6v vih 70 % dvdd - - v 1.6v dvdd<2.2v vih 80 % dvdd - - v low-level input voltage 2.2v dvdd 3.6v vil - - 30 % dvdd v 1.6v dvdd<2.2v vil - - 20 % dvdd v input voltage at ac coupling ( note 21) vac 0.4 - - vpp high-level output voltage (iout= ? 200 a) voh dvdd ? 0.2 - - v low-level output voltage (except sda pin: iout=200 a) vol - - 0.2 v (sda pin, 2.0v dvdd 3.6v: iout=3ma) vol - - 0.4 v (sda pin, 1.6v dvdd<2.0v: iout=3ma) vol - - 20%dvdd v input leakage current iin - - 10 a note 21. mcki is connected to a capacitor. (refer to figure 38)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 11 - switching characteristics (ta=25 c; avdd, dvdd, hvdd=1.6 3.6v; c l = 20pf; unless otherwise specified) parameter symbol min typ max units master clock input timing frequency fclk 2.048 - 24.576 mhz pulse width low ( note 22) tclkl 0.4/fclk - - ns pulse width high ( note 22) tclkh 0.4/fclk - - ns ac pulse width ( note 23) tacw 20.3 - - ns lrck timing frequency fs 8 44.1 48 khz duty cycle: slave mode duty 45 - 55 % master mode duty - 50 - % serial interface timing ( note 24) slave mode (m/s bit = ?0?): bick period ( note 25) tbck 312.5 or 1/(64fs) - 1/(32fs) ns bick pulse width low tbckl 100 - - ns pulse width high tbckh 100 - - ns lrck edge to bick ? ? ( note 26) tlrb 50 - - ns bick ? ? to lrck edge ( note 26) tblr 50 - - ns sdata hold time tsdh 50 - - ns sdata setup time tsds 50 - - ns master mode (m/s bit = ?1?): bick frequency (bf bit = ?1?) fbck - 64fs - hz (bf bit = ?0?) fbck - 32fs - hz bick duty dbck - 50 - % bick ? ? to lrck tmblr ? 50 - 50 ns sdata hold time tsdh 50 - - ns sdata setup time tsds 50 - - ns control interface timing (3-wire serial mode) cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn ? ? to cclk ? ? tcss 50 - - ns cclk ? ? to csn ? ? tcsh 50 - - ns note 22. except ac coupling. note 23. pulse width to ground level when mcki is connected to a capacitor in series and a resistor is connected to ground. (refer to figure 3.) note 24. refer to ?serial data interface?. note 25. min is longer value between 312.5ns or 1/(64fs) except for pll mode, pll4-0 bits = ?eh?, ?fh?. note 26. bick rising edge must not occur at the same time as lrck edge.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 12 - parameter symbol min typ max units control interface timing (i 2 c bus mode): ( note 27) scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 28) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppressed by input filter tsp 0 - 50 ns power-down & reset timing pdn pulse width ( note 29) tpd 150 - - ns note 27. i 2 c is a registered trademark of philips semiconductors. note 28. data must be held long enough to bridge the 300ns-transition time of scl. note 29. the ak4370 can be reset by bringing pdn pin = ?l? to ?h? only upon power up.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 13 - timing diagram mcki input measurement point vss2 tacw t acw vss2 1/fclk 1000pf 100k vac figure 3. mcki ac coupling timing 1/fclk tclkl vih tclkh mcki vil 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 4. clock timing
asahi kasei [ak4370] ms0595-e-00 2007/03 - 14 - tlrb lrck vih bick vil tsds vih sdata vil tsdh vih vil tblr figure 5. serial interf ace timing (slave mode) lrck 50%dvdd bick tsds vih sdata vil tsdh 50%dvdd tmblr figure 6. serial interf ace timing (master mode)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 15 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh figure 7. write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh figure 8. write data input timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 9. i 2 c bus mode timing tpd vil pdn figure 10. power-down & reset timing
asahi kasei [ak4370] ms0595-e-00 2007/03 - 16 - operation overview system clock the ak4370 supports both master and slave mode s to interface with external devices. (see table 1). the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak4370 is power-down mode (pdn pin = ?l?) and exits reset st ate, the ak4370 is slave mode. after exiting reset state, the ak4370 goes to master mode by changing m/s bit = ?1?. when the ak4370 is used by master mode, lrck and bick pins are a floating state until m/s bit becomes ?1?. lrck and bick pins of the ak4370 should be pulled-down or pulled-up by the resistor (about 100k ) externally to avoid the floating state. m/s bit mode mcki pin bick pin lrck pin figure 1 master mode selected by fs3-0 bits output (selected by bf bit) output (1fs) figure 11 0 slave mode selected by fs3-0 bits input (32fs 64fs) input (1fs) figure 12 default table 1. clock mode setting (x: don?t care) the frequency of master clock inputted to the mcki pin can be selected fs3-0 bits. (refer to table 2) if the sampling frequency is changed duri ng normal operation of the dac (pmdac bit = ?1?), the change should occur after the input is muted by smute bit = ?1?, or the input is set to ?0? data. lrck and bick are output from the ak4370 in master mode ( figure 11). the clock input to the mcki pin should always be present whenever the dac is in normal operation (pmdac bit = ?1?). if these clocks are not provided, the ak4370 may draw excessive current and w ill not operate properly because it utilizes these clocks for internal dynamic refresh of registers. if the external cl ocks are not present, the dac should be placed in power-down mode (pmdac bit = ?0?). ak4370 dsp or p mcki bick lrck sdata bclk lrck sdto 1fs 32fs, 64fs mclk 256fs, 384fs, 512fs, 768fs or 1024fs figure 11. master mode
asahi kasei [ak4370] ms0595-e-00 2007/03 - 17 - the external clocks required to operate the ak4370 in slave mode are mcki, lrck and bick ( figure 12). the master clock (mcki) should be synchronized with the sampling clock (lrck). the phase between these clocks does not matter. all external clocks (mcki, bick and lrck) should always be present whenever the dac is in normal operation mode (pmdac bit = ?1?). if these clocks are not provided, th e ak4370 may draw excessive cu rrent and will not operate properly, because it utilizes these clocks fo r internal dynamic refresh of registers. if the external clocks are not present, t he dac should be placed in power- down mode (pmdac bit = ?0?). ak4370 dsp or p mcki bick lrck sdata bclk lrck sdto 1fs 32fs ~ 64fs mclk 256fs, 384fs, 512fs, 768fs or 1024fs figure 12. slave mode mode fs3 fs2 fs1 fs0 fs mcki 0 0 0 0 0 8khz 48khz 256fs 1 0 0 0 1 8khz 48khz 512fs 2 0 0 1 0 8khz 24khz 1024fs 4 0 1 0 0 8khz 48khz 256fs 5 0 1 0 1 8khz 48khz 512fs 6 0 1 1 0 8khz 24khz 1024fs 8 1 0 0 0 8khz 48khz 256fs default 9 1 0 0 1 8khz 48khz 512fs 10 1 0 1 0 8khz 24khz 1024fs 12 1 1 0 0 8khz 48khz 384fs 13 1 1 0 1 8khz 24khz 768fs others others n/a n/a table 2. relationship between samp ling frequency and mcki frequency master mode (m/s bit = ?1?) power up (pmdac bit = ?1?) power down (pmdac bit = ?0?) mcki pin refer to table 2 input or fixed to ?l? or ?h? externally bick pin bf bit = ?1?: 64fs output bf bit = ?0?: 32fs output ?l? lrck pin output ?l? table 3. clock operation in master mode
asahi kasei [ak4370] ms0595-e-00 2007/03 - 18 - slave mode (m/s bit = ?0?) power up (pmdac bit = ?1?) po wer down (pmdac bit = ?0?) mcki pin refer to table 2 input or fixed to ?l? or ?h? externally bick pin input fixed to ?l? or ?h? externally lrck pin input fixed to ?l? or ?h? externally table 4. clock operation in slave mode for low sampling rates, dr and s/n degrade because of th e out-of-band noise. dr and s/n are improve d by using higher frequency for mcki. table 5 shows dr and s/n when the dac output is to the hp-amp. dr, s/n (bw=20khz, a-weight) mcki fs=8khz fs=16khz 256fs/384fs/512fs 56db 75db 768fs/1024fs 75db 90db table 5. relationship between mcki frequenc y and dr (and s/n) of hp-amp (2.4v)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 19 - serial data interface the ak4370 interfaces with external system s via the sdata, bick and lrck pins . five data formats are available, selected by setting the dif2, dif1 and dif0 bits ( table 6). mode 0 is compatible with existing 16-bit dacs and digital filters. mode 1 is a 20-bit version of mode 0. mode 4 is a 24-bit version of mode 0. mode 2 is similar to akm adcs and many dsp serial ports. mode 3 is compatible with the i 2 s serial data protocol. in modes 2 and 3 with bick 48fs, the following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st to 24th bits). in all modes, the serial data is msb first and 2?s complement format. when master mode and bick=32fs(bf bit = ?0?), the ak4370 cannot be set to mode 1, mode 2 and mode4. mode dif2 dif1 dif0 format bick figure 0 0 0 0 0: 16bit, lsb justified 32fs bick 64fs figure 13 1 0 0 1 1: 20bit, lsb justified 40fs bick 64fs figure 14 2 0 1 0 2: 24bit, msb justified 48fs bick 64fs figure 15 default 3 0 1 1 3: i 2 s compatible bick=32fs or 48fs bick 64fs figure 16 4 1 0 0 4: 24bit, lsb justified 48fs bick 64fs figure 14 table 6. audio data format sdata bick lrck sdata 15 14 6 5 4 bick 3 2 1 0 15 14 ( 32fs ) 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 13. mode 0 timing (lrp = bckp bits = ?0?) sdata lrck bick 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdata mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 23 23 figure 14. mode 1, 4 timing (lrp = bckp bits = ?0?)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 20 - lrck bick sdata 16bit don?t 0 14 15 14 15 lch rch care 14 0 15 sdata 20bit 18 19 18 19 4 1 0 don?t care 18 19 410 don?t care don?t care sdata 24bit 22 23 22 23 don?t care 22 23 don?t care 8 3 4 0 1 83 4 0 1 figure 15. mode 2 timing (lrp = bckp bits = ?0?) lrck lch rch bick don?t 0 14 15 15 care 14 0 15 19 18 19 4 1 0 don?t care 18 19 41 0 don?t care don?t care sdata 16bit sdata 20bit sdata 24bit 23 22 23 don?t care 22 23 don?t care 8 3 4 0 1 83 4 0 1 bick 6 14 15 15 14 6 15 sdata 16bit ( 32fs ) 0 5 4 321 0 54 3 2 1 0 figure 16. mode 3 timing (lrp = bckp bits = ?0?)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 21 - digital attenuator the ak4370 has a channel-independent digita l attenuator (256 levels, 0.5db step). th is digital attenuator is placed before the d/a converter. attl/r7-0 bits set the attenuation level (0db to ? 127db or mute) for each channel ( table 7). at dattc bit = ?1?, attl7-0 bits control both channel?s attenuation levels. at da ttc bit = ?0?, attl7-0 bits control the left channel level and attr7-0 bits control the right channel level. attl7-0 attr7-0 attenuation ffh 0db feh ? 0.5db fdh ? 1.0db fch ? 1.5db : : : : 02h ? 126.5db 01h ? 127.0db 00h mute ( ? ) default table 7. digital volume att values the ats bit sets the transition time between set values of att7-0 bits as either 1061/fs or 7424/fs ( table 8). when the ats bit = ?0?, a soft transition between the set values occurs(1062 levels). it takes 1061/fs (24ms@fs=44.1khz) from ffh(0db) to 00h(mute). the atts are 00h when the pmdac bit is ?0?. when the pmdac returns to ?1?, the atts fade to their current value. the digital attenua tor is independent of the soft mute function. att speed ats 0db to mute 1 step 0 1061/fs 4/fs default 1 7424/fs 29/fs table 8. transition time between set values of att7-0 bits
asahi kasei [ak4370] ms0595-e-00 2007/03 - 22 - soft mute soft mute operation is performed in the digital domain. when the smute bit goes to ?1?, the output signal is attenuated by ? during the att_data att transition time ( table 8) from the current att level. when the smute bit is returned to ?0?, the mute is can celled and the output attenuation gradua lly changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and is returned to the att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation ats bit att level - a nalog output gd gd (1) (2) (3) ats bit (1) figure 17. soft mute function notes: (1) att_data att transition time ( table 8). for example, this time is 3712lrck cycles (3712/fs) at ats bit = ?1? and att_data = ?128? (-63.5db). (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and it is returned to the att level by the same cycle.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 23 - de-emphasis filter the ak4370 includes a digital de -emphasis filter (tc = 50/15 s), using an iir filter co rresponding to three sampling frequencies (32khz, 44.1khz and 48khz). the de-emphasi s filter is enabled by setting dem1-0 bits ( table 9). dem1 bit dem0 bit de-emphasis 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 9. de-emphasis filter frequency select bass boost function by controlling the bst1-0 bits, a low frequency boost signa l can be output from dac. the setting value is common for both channels ( table 10). bst1 bit bst0 bit boost 0 0 off default 0 1 min 1 0 mid 1 1 max table 10. low frequency boost select digital mixing function mono1-0 bits select the digital data mixing for the dac ( table 11). mono1 bit mono0 bit lch rch 0 0 l r default 0 1 l l 1 0 r r 1 1 (l+r)/2 (l+r)/2 table 11. mixer setting system reset pdn pin should be held to ?l? upon power-up. the 4370 should be reset by bringing pdn pin ?l? for 150ns or more. all of the internal register values are initialized by the system reset. after exiting reset, vcom, dac, hpl, hpr, lout and rout switch to the power-down state. the contents of the control register are maintained until the reset is completed. the dac exits reset and power down states by mcki after the pmdac bit is changed to ?1?. the dac is in power-down mode until mcki is input.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 24 - headphone output (hpl, hpr pins) the power supply voltage for the headphone-amp is supp lied from the hvdd pin and is centered on the mutet voltage. the headphone-amp output load resistance is 16 (min). when the muten bit is ?1? at pmhpl=pmhpr= ?1?, the common voltage rises to 0.475 x avdd. when the muten bit is ?0?, the common voltage of the headphone-amp falls and the outputs (hpl and hpr pins) go to vss1. t r : rise time up to vcom/2 70k x c (typ) t f : fall time down to vcom/2 60k x c (typ) table 12. headphone-amp rise/fall time [example] : capacitor between the mutet pin and ground = 1 f: rise time up to vcom/2: t r = 70k x 1 = 70ms (typ). fall time down to vcom/2: t f = 60k x 1 = 60ms (typ). when the pmhpl and pmhpr bits are ?0?, the headphone-amp is powered-down, and the outputs (hpl and hpr pins) go to vss1. muten bit pmhpl/r bit hpl/r pin (1) (2) (4) (3) t r t f vcom/2 vcom figure 18. power-up/power-down timing for the headphone-amp (1) headphone-amp power-up (pmhpl and pmhpr b its = ?1?). the outputs are still at vss1. (2) headphone-amp common voltage rises up (muten bit = ?1?). common voltage of the headphone-amp is rising. this rise time depends on the capacitor value connected with the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ) when the capacitor value on mutet pin is ?c?. (3) headphone-amp common voltage falls down (muten bit = ?0?). common voltage of the headphone-amp is falling to vss1. this fall time depends on the capacitor value connect ed with the mutet pin. the fall time down to vcom/2 is t f = 60k x c(typ) when the capacitor value on mutet pin is ?c?. (4) headphone-amp power-down (pmhpl, pmhpr bits = ?0?). the outputs are at vss1. if the power supply is switched off or the headphone-amp is powered-down before the common voltage goes to vss1, some pop noise may occur.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 25 - < external circuit of headphone-amp > the cut-off frequency of the headphone-amp output depe nds on the external resistor and capacitor used. table 13 shows the cut off frequency and the output power for various re sistor/capacitor combinations. the headphone impedance r l is 16 . output powers are shown at avdd = 2.4, 3.0 and 3.3v. the output voltage of the headphone-amp is 0.48 x avdd (vpp) @ ? 3dbfs. ak4370 hp-amp 16 headphone r c figure 19. external circuit example of headphone output power [mw] r [ ] c [ f] fc [hz] boost=off fc [hz] boost=min 2.4v 3.0v 3.3v 220 45 17 0 100 100 43 21 33 40 100 70 28 6.8 47 149 78 10 16 20 100 50 19 16 47 106 47 5 8 10 table 13. relationship of external circ uit, output power and frequency response < wired or with external headphone-amp > when pmvcm=pmhpl=pmhpr bits = ?0? and hpz bit = ?1?, headphone-amp is powered-down and hpl/r pins are pulled-down to vss1 by 200k (typ). in this setting, it is available to connect headphone-amp of ak4370 and external single supply headphone-amp by ?wired or?. pmvcm pmhpl/r hpmtn hpz mode hpl/r pins x 0 x 0 power-down & mute vss1 default 0 0 x 1 power-down pull-down by 200k 1 1 0 x mute vss1 1 1 1 x normal operation normal operation table 14. hp-amp mode setting (x: don?t care) hpl pin hpr pin headphone ak4370 anothe r hp-amp figure 20. wired or with external hp-amp
asahi kasei [ak4370] ms0595-e-00 2007/03 - 26 - < analog mixing circuit for headphone output > dalhl, lin1hl, rin1hl, lin2hl and rin2hl bits c ontrol each path switch of hpl output. darhr, lin1hr, rin1hr, lin2hr and rin2hr bits cont rol each path switch of hpr output. when l1hm=l2hm bits = ?0?, hpg1-0 bits = ?00? (r 1h = r 2h = r dh = 100k) and atth4-0 bits = ?00h? (0db), the mixing gain is +0.95db (typ). when hpg1-0 bit = ?01? (r dh = 50k), the mixing gain of dac path is +6.95db (typ). when hpg1-0 bit = ?10? (r dh = 25k), the mixing gain of dac path is +12.95db (typ). when l1hm and l2hm bits are ?1?, lin1/rin1 and lin2/rin2 signals are output from hpl/r pins as (l+r)/2, respectively (r 1h = r 2h = 200k). when ldif=ldifh=lin1l=rin1r bits = ?1?, lin1 and rin1 pins becomes in+ and in ? pins, respectively. in+ and in ? pins can be used as full-differential mono line input for analog mixing for headphone-amp. in this case, lin1hl, rin1hl, lin1hr and rin1hr bits should be ?0?. if the path is off and the signal is input to the input pin, th e input pin should be biased to a voltage equivalent to vcom voltage (= 0.475 x avdd) externally. figure 39 shows the external bias circuit example. ? + hpl pin hp-amp 1.11r h r dh dalhl bit ? + 100k(typ) r h rin2 pin r 2h rin2hl bit lin2 pin r 2h lin2hl bit dac lch rin1 pin r 1h rin1hl bit lin1 pin r 1h lin1hl bit figure 23 100k(typ) ldifh bit ? + hpr pin hp-amp 1.11r h r dh darhr bit ? + 100k(typ) r h rin2 pin r 2h rin2hr bit lin2 pin r 2h lin2hr bit dac rch rin1 pin r 1h rin1hr bit lin1 pin r 1h lin1hr bit figure 23 100k(typ) ldifh bit figure 21. summation circuit for hpl/r output
asahi kasei [ak4370] ms0595-e-00 2007/03 - 27 - headphone output volume hpl/hpr volume is controlled by atth4-0 bit when hmute bit = ?0? (+12db ? 51db or +6db ? 57db or 0db ? 63db, 1.5db or 3db step, table 15) hmute atth4-0 hpg1-0 bits = ?10? (dac only) hpg1-0 bits = ?01? (dac only) hpg1-0 bits = ?00? step 00h +12db +6db 0db default 01h +10.5db +4.5db ? 1.5db 02h +9db +3db ? 3db 03h +7.5db +1.5db ? 4.5db : : : : 1.5db : : : : 12h ? 15db ? 21db ? 27db 13h ? 16.5db ? 22.5db ? 28.5db 14h ? 18db ? 24db ? 30db 15h ? 21db ? 27db ? 33db 16h ? 24db ? 30db ? 36db : : : : : : : : 3db 1dh ? 45db ? 51db ? 57db 1eh ? 48db ? 54db ? 60db 0 1fh ? 51db ? 57db ? 63db 1 x mute mute mute table 15. hpl/hpr volume att values (x: don?t care)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 28 - stereo line output (lout, rout pins) the common voltage is 0.475 x avdd. the load resistance is 10k (min). when the pmlo bit is ?1?, the stereo line output is powered-up. dall, lin1l, rin1l, lin2l and rin2 l bits control each path sw itch of lout. darr, lin1r, rin1r, lin2r and rin2r bits control each path switch of rout. when l1m = l2m bits = ?0?, log bit = ?0? (r 1l = r 2l = r dl = 100k) and atts3-0 bits is ?0fh?(0db), the mixing gain is 0db(typ) for all paths. when the log bit = ?1?(r dl = 50k), the dac path gain is +6db. when l1m = l2m bits = ?1?, lin1/rin1 and lin2/rin2 signals are output from lout/rout pins as (l+r)/2, respectively (r 1l = r 2l = 200k). if the path is off and the signal is input to the input pin, th e input pin should be biased to a voltage equivalent to vcom voltage (= 0.475 x avdd) externally. figure 39 shows the external bias circuit example. ? + lout pin r l r dl dall bit ? + 100k(typ) r l rin2 pin r 2l rin2l bit lin2 pin r 2l lin2l bit dac lch rin1 pin r 1l rin1l bit lin1 pin r 1l lin1l bit ? + rout pin r l darr bit ? + 100k(typ) r l dac rch r dl rin2 pin r 2l rin2r bit lin2 pin r 2l lin2r bit rin1 pin r 1l rin1r bit lin1 pin r 1l lin1r bit figure 22. summation circuit for stereo line output
asahi kasei [ak4370] ms0595-e-00 2007/03 - 29 - < analog mixing circuit of full-differential mono input > when ldif=lin1l=rin1r bits = ?1?, lin1 and rin1 pins becomes in+ and in ? pins, respectively. in+ and in ? pins can be used as full-differential mono line input for analog mi xing of lout/rout pins. it is not available to mix with other signal source for lout/rout outputs. if the path is off and the signal is input to the input pin, th e input pin should be biased to a voltage equivalent to vcom voltage (= 0.475 x avdd) externally. figure 39 shows the external bias circuit example. ? + lout pin in ? p in r l 100k(typ) r 1l lin1l bit ldif bit ? + 100k(typ) r l ? + rout pin r l r l in+ pin r 1l rin1r bit ? + 100k(typ) hpl/r pins ldifh bit figure 21 figure 23. summation circuit for stereo line output (full-differential input, log bit = ?0?) v stereo line output (lout/rout pins) volume lout/rout volume is controlled by atts3-0 bits when lmute bit = ?0? (+6db ? 24db or 0db ? 30db, 2db step, table 16). pop noise occurs when atts3-0 bits are changed. lmute atts3-0 log bit = ?1? (dac only) log bit = ?0? fh +6db 0db eh +4db ? 2db dh +2db ? 4db ch 0db ? 6db : : : : : : 1h ? 22db ? 28db 0 0h ? 24db ? 30db 1 x mute mute default table 16. lout/rout volume att values (x: don?t care)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 30 - power-up/down sequence 1) dac hp-amp power supply pdn pin pmvcm bit clock input (3) sdti pin pmdac bit dac internal state pd normal operation hpl/r pin pmhpl, pmhpr bits (6) a ttl7-0 a ttr7-0 bits 00h(mute) ffh(0db) (8) gd (9) 1061/fs pd normal operation 00h(mute) ffh(0db) (8) (9) (6) (7) (8) (9) don?t care don?t care (7) (8) (9) 00h(mute) don?t care (10) don?t care (1) >150ns (2) >0s pd (5) >2ms muten bit dalhl, darhr bits (4) >0s (4) >0s (5) >2ms figure 24. power-up/down sequence of dac and hp-amp (don?t care: except hi-z) (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. when avdd and hvdd are supplied separately, avdd should be powered-up at the same time or earlier than hvdd. pdn pin should be set to ?h? at least 150ns after power is supplied. (2) pmvcm and pmdac bits should be changed to ?1? after pdn pin goes ?h?. (3) external clocks (mcki, bick, lrck) are needed to operate the dac. when the pmdac bit = ?0?, these clocks can be stopped. the headphone-amp can operate without these clocks. (4) dalhl and darhr bits should be changed to ?1? after pmvcm and pmdac bit is changed to ?1?. (5) pmhpl, pmhpr and muten bits should be changed to ?1? at least 2ms (in case external capacitance at vcom pin is 2.2 f) after the dalhl and darhr bits are changed to ?1? (6) rise time of the headphone-amp is determined by an exte rnal capacitor (c) of the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ). when c=1 f, t r = 70ms(typ). (7) fall time of the headphone-amp is determined by an exte rnal capacitor (c) of the mu tet pin. the fall time down to vcom/2 is t f = 60k x c(typ). when c=1 f, t f = 60ms(typ). pmhpl and pmhpr bits should be changed to ?0? after hp l and hpr pins go to vss1. after that, the dalhl and darhr bits should be changed to ?0?. (8) analog output corresponding to the digital input ha s a group delay (gd) of 22/fs(=499s@fs=44.1khz). (9) the ats bit sets transition time of digital atte nuator. default value is 1061/fs(=24ms@fs=44.1khz). (10) the power supply should be switched off after the hea dphone-amp is powered down (hpl/r pins become ?l?). when avdd and dvdd are supplied separately, dvdd should be powered-down at the same time or later than avdd. when avdd and hvdd are supplied separately, avdd should be powered-down at the same time or later than hvdd.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 31 - 2) dac lineout power supply pdn pin pmvcm bit clock input (5) sdti pin pmdac bit dac internal state pd(power-down) normal operation pmlo bit a ttl/r7-0 bits 00h(mute) ffh(0db) lout/rout pins (6) lmute, a tts3-0 bits 10h(mute) 0fh(0db) (7) gd (8) 1061/fs (hi-z) pd normal operation 00h(mute) ffh(0db) (hi-z) (7) (8) (6) (6) (7) (8) don?t care don?t care don?t care (1) >150ns (2) >0s (4) >0s dall, darr bits (3) >0s figure 25. power-up/down sequence of dac and lout/rout (don?t care: except hi-z) (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. when avdd and hvdd are supplied separately, avdd should be powered-up at the same time or earlier than hvdd. pdn pin should be set to ?h? at least 150ns after power is supplied. (2) pmvcm bit should be changed to ?1? after the pdn pin goes ?h?. (3) dall and darr bits should be changed to ?1? after the pmvcm bit is changed to ?1?. (4) pmdac and pmlo bits should be changed to ?1? after dall and darr bits is changed to ?1?. (5) external clocks (mcki, bick, lrck) are needed to operate the dac. when the pmdac bit = ?0?, these clocks can be stopped. the lout/rout buffer can operate without these clocks. (6) when the pmlo bit is changed, pop noise is output from lout/rout pins. (7) analog output corresponding to the digital input has a group delay (gd) of 22fs(=499 s@fs=44.1khz). (8) the ats bit sets the transition time of the digital attenuator. default value is 1061/fs(=24ms@fs=44.1khz).
asahi kasei [ak4370] ms0595-e-00 2007/03 - 32 - 3) lin1/rin1/lin2/rin2 hp-amp power supply pdn pin pmvcm bit hpl/r pins (6) (6) (7) lin1/rin1/ lin2/rin2 pins (4) (hi-z) (hi-z) pmhpl/r bits don?t care (1) >150ns (2) >0s muten bit lin1hl, lin2hl, rin1hr, rin2hr bits (3) >0s (5) >2ms (5) >2ms figure 26. power-up/down sequence of lin1/rin1/lin2/rin2 and hp-amp (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. when avdd and hvdd are supplied separately, avdd should be powered-up at the same time or earlier than hvdd. pdn pin should be set to ?h? at least 150ns after power is supplied. mcki, bick and lrck can be stopped when dac is not used. (2) pmvcm bit should be changed to ?1? after pdn pin goes ?h?. (3) lin1hl, lin2hl, rin1hr and rin2hr bits should be changed to ?1? after pmvcm bit is changed to ?1?. (4) when lin1hl, lin2hl, rin1hr or rin2hr bit is changed to ?1?, lin1, rin1, lin2 or rin2 pin is biased to 0.475 x avdd. (5) pmhpl, pmhpr and muten bits should be changed to ?1? at least 2ms (in case external capacitance at vcom pin is 2.2 f) after lin1hl, lin2hl, rin1hr and rin2hr bits are changed to ?1?. (6) rise time of the headphone-amp is determined by an exte rnal capacitor (c) of the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ). when c=1 f, t r = 70ms(typ). (7) fall time of the headphone-amp is determined by an exte rnal capacitor (c) of the mu tet pin. the fall time down to vcom/2 is t f = 60k x c(typ). when c=1 f, t f = 60ms(typ). pmhpl and pmhpr bits should be changed to ?0? after hpl and hpr pins go to vss1. after that, the lin1hl, lin2hl, rin1hr and rin2hr bits should be changed to ?0?.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 33 - 4) lin1/rin1/lin2/rin2 lineout power supply pdn pin pmvcm bit lmute, a tts3-0 bits 10h(mute) 0fh(0db) lin1/rin1/ lin2/rin2 pins (4) (hi-z) (hi-z) pmlo bit don?t care (1) >150ns (2) >0s lin1l, rin1r, lin2l, rin2r bits (3) >0s (5) >2ms (5) >2ms lout/rout pins (6) (hi-z) (hi-z) (6) (6) figure 27. power-up/down sequence of lin1/rin1/lin2/rin2 and lineout (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. when avdd and hvdd are supplied separately, avdd should be powered-up at the same time or earlier than hvdd. pdn pin should be set to ?h? at least 150ns after power is supplied. mcki, bick and lrck can be stopped when dac is not used. (2) pmvcm bit should be changed to ?1? after pdn pin goes ?h?. (3) lin1l, lin2l, rin1r and rin2r bits should be changed to ?1? after pmvcm bit is changed to ?1?. (4) when lin1l, lin2l, rin1r or rin2r bit is changed to ?1?, lin1, rin1, lin2 or rin2 pin is biased to 0.475 x avdd. (5) pmlo bit should be changed to ?1? at least 2ms (in case external capacitance at vcom pin is 2.2 f) after lin1l, lin2l, rin1r and rin2r b its are changed to ?1?. (6) when the pmlo bit is changed, pop noise is output from lout/rout pins.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 34 - serial control interface (1) 3-wire serial control mode (i2c pin = ?l?) internal registers may be written to via the 3-wire p interface pins (csn, cclk and cdti). the data on this interface consists of the chip address (2-bits, fixed to ?01?), read/wr ite (1-bit, fixed to ?1?, write only), register address (msb first, 5-bits) and control data (msb first, 8-bits). address and data are clocked in on the rising edge of cclk. for write operations, the data is latched after a low-to-high transition of the 16th cclk. csn should be set to ?h? once after 16 cclks for each address. the clock speed of cclk is 5mhz(max ). the value of the internal registers is initialized at pdn pin = ?l?. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (fixed to ?01?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 28. 3-wire serial control i/f timing
asahi kasei [ak4370] ms0595-e-00 2007/03 - 35 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4370 supports fast-mode i 2 c-bus (max: 400khz, version 1.0). (2)-1. write operations figure 29 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 35). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant six bits of the slave address are fixed as ?001000?. the next bit is cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) sets this device address bit ( figure 30). if the slave address matches that of the ak4370, th e ak4370 generates an acknowledgement and the operation is executed. the master must generate the acknowledge-relate d clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 36). a r/w bit value of ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4370. the format is msb first, and those most significant 3-bits are fixed to zeros ( figure 31). the data after the second byte contains control data. the format is msb first, 8bits ( figure 32). the ak4370 generates an acknow ledgement after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 35). the ak4370 can perform more than one byte write operati on per sequence. after receiving the third byte the ak4370 generates an acknowledgement and awaits the next data. th e master can transmit more than one byte instead of terminating the write cycle after the first data byte is tran sferred. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 13h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cl ock signal on the scl line is low( figure 37) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 29. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 cad0 r/w (those cad0 should match with cad0 pin) figure 30. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 31. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 32. byte structure after the second byte
asahi kasei [ak4370] ms0595-e-00 2007/03 - 36 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the ak4370. after a transmission of data, the master can read the next address?s data by generating an acknowle dge instead of terminating the writing cy cle after receiving the first data word. after receiving each data packet the inte rnal 5-bit address counter is increm ented by one, and the next data is automatically taken into the next address. if the address exceeds 13h prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the ak4370 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the ak4370 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receiving the slave a ddress with r/w bit set to ?1?, the ak4370 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledgement to the data but instead generates a stop condition, the ak4370 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 33. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the ak4370 then generates an acknowledgement, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledgement to the data but instead generate s a stop condition, the ak4370 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 34. random address read
asahi kasei [ak4370] ms0595-e-00 2007/03 - 37 - scl sda stop condition start condition s p figure 35. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 36. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 37. bit transfer on the i 2 c-bus
asahi kasei [ak4370] ms0595-e-00 2007/03 - 38 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 0 0 pmlo muten pmhpr pmhpl pmdac pmvcm 01h clock control 0 fs3 fs2 fs1 fs0 0 0 0 0 02h clock control 1 0 0 m/s mckac bf 0 0 0 03h mode control 0 0 mono1 mono0 bckp lrp dif2 dif1 dif0 04h mode control 1 ats dattc lmute smute bst1 bst0 dem1 dem0 05h dac lch att attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 06h dac rch att attr7 attr6 attr5 attr4 a ttr3 attr2 attr1 attr0 07h headphone out select 0 hpg1 hpg0 lin2hr lin2hl rin1hr lin1hl darhr dalhl 08h lineout select 0 0 log lin2r lin2l rin1r lin1l darr dall 09h lineout att 0 0 0 0 atts3 atts2 atts1 atts0 0ah reserved 0 0 0 0 0 0 0 0 0bh reserved 0 0 0 0 0 0 0 0 0ch reserved 0 0 0 0 0 0 0 0 0dh headphone out select 1 0 0 0 0 rin2hr rin2hl lin1hr rin1hl 0eh headphone att 0 hpz hmute atth4 atth3 atth2 atth1 atth0 0fh lineout select 1 0 0 0 0 rin2r rin2l lin1r rin1l 10h mono mixing 0 0 0 0 l2m l2hm l1m l1hm 11h differential select 0 0 0 0 0 0 ldifh ldif 12h reserved 0 0 0 0 0 0 0 0 13h reserved 0 0 0 1 0 0 0 0 all registers inhibit writ ing at pdn pin = ?l?. pdn pin = ?l? resets the registers to their default values. for addresses from 14h to 1fh, data must not be written. unused bits must contain a ?0? value. unused bits must contain a ?1? value
asahi kasei [ak4370] ms0595-e-00 2007/03 - 39 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 0 0 0 pmlo muten pmhpr pmhpl pmdac pmvcm r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmvcm: power management for vcom block 0: power off (default) 1: power on pmdac: power management for dac blocks 0: power off (default) 1: power on when the pmdac bit is changed from ?0? to ?1?, the dac is powered-up to the current register values (att value, sampling rate, etc). pmhpl: power management for the left channel of the headphone-amp 0: power off (default). hpl pin goes to vss1(0v). 1: power on pmhpr: power management for the right channel of the headphone-amp 0: power off (default). hpr pin goes to vss1(0v). 1: power on muten: headphone amp mute control 0: mute (default). hpl and hpr pins go to vss1(0v). 1: normal operation. hpl and hpr pins go to 0.475 x avdd. pmlo: power management for stereo output 0: power off (default) l out/rout pins go to hi-z. 1: power on each block can be powered-down respectiv ely by writing ?0? in each bit of this address. wh en the pdn pin is ?l?, all blocks are powered-down regardless as setting of this addr ess. in this case, register is initialized to the default value. when pmvcm, pmdac, pmhpl, pmhpr a nd pmlo bits are ?0?, all blocks are powered-down. the register values remain unchanged. power supply current is 20 a(typ) in this case. for fully shut down (typ. 1 a), pdn pin should be ?l?.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 40 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h clock control 0 fs3 fs2 fs1 fs0 0 0 0 0 r/w r/w r/w r/w r/w rd rd rd rd default 1 0 0 0 0 0 0 0 fs3-0: sampling frequency select see table 2. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock control 1 0 0 m/s mckac bf 0 0 0 r/w rd rd r/w r/w r/w rd rd rd default 0 0 0 0 0 0 0 0 bf: bick period setting in master mode. in slave mode, this bit is ignored. 0: 32fs (default) 1: 64fs mckac: mcki input mode select 0: cmos input (default) 1: ac coupling input m/s: master/slave mode select 0: slave mode (default) 1: master mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h mode control 0 0 mono1 mono0 bckp lrp dif2 dif1 dif0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 dif2-0: audio data interface format select ( table 6) default: ?010? (mode 2) lrp: lrck polarity select in slave mode 0: normal (default) 1: invert bckp: bick polarity select in slave mode 0: normal (default) 1: invert mono1-0: mixing select ( table 11) default: ?00? (lr)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 41 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 ats dattc lmute smute bst1 bst0 dem1 dem0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 0 0 0 0 1 dem1-0: de-emphasis filter frequency select ( table 9) default: ?01? (off) bst1-0: low frequency boost function select ( table 10) default: ?00? (off) smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted lmute: mute control for lout/rout ( note 19) 0: normal operation. atts3-0 bits control attenuation value. 1: mute. atts3-0 bits are ignored. (default) dattc: dac digital attenuator control mode select 0: independent (default) 1: dependent at dattc bit = ?1?, attl7-0 bits control both channel attenuation le vels, while register values of attl7-0 bits are not written to the attr7-0 bits. at dattc bit = ?0?, the attl7-0 bits control the left channel level and the attr7-0 bits control the right channel level. ats: digital attenuator transition time setting ( table 8) 0: 1061/fs (default) 1: 7424/fs addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h dac lch att attl7 attl6 attl5 attl4 a ttl3 attl2 attl1 attl0 06h dac rch att attr7 attr6 attr5 attr4 a ttr3 attr2 attr1 attr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 attl7-0: setting of the attenuation value of output signal from dacl ( table 7) attr7-0: setting of the attenuation value of output signal from dacr ( table 7) default: ?00h? (mute)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 42 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h headphone out select 0 hpg1 hpg0 lin2hr lin2hl rin1hr lin1hl darhr dalhl r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dalhl: dac left channel output signal is adde d to the left channel of the headphone-amp. 0: off (default) 1: on darhr: dac right channel output signal is adde d to the right channel of the headphone-amp. 0: off (default) 1: on lin1hl: input signal to lin1 pin is added to the left channel of the headphone-amp. 0: off (default) 1: on rin1hr: input signal to rin1 pin is added to the right channel of the headphone-amp. 0: off (default) 1: on lin2hl: input signal to lin2 pin is added to the left channel of the headphone-amp. 0: off (default) 1: on lin2hr: input signal to lin2 pin is added to the right channel of the headphone-amp. 0: off (default) 1: on hpg1-0: dac ? hpl/r gain ( note 18) default: ?00?: +0.95db
asahi kasei [ak4370] ms0595-e-00 2007/03 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h lineout select 0 0 log lin2r lin2l rin1r lin1l darr dall r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dall: dac left channel output is added to the lout buffer amp. 0: off (default) 1: on darr: dac right channel output is added to the rout buffer amp. 0: off (default) 1: on lin1l: input signal to the lin1 pin is added to the lout buffer amp. 0: off (default) 1: on rin1r: input signal to the rin1 pin is added to the rout buffer amp. 0: off (default) 1: on lin2l: input signal to the lin2 pin is added to the lout buffer amp. 0: off (default) 1: on lin2r: input signal to the lin2 pin is added to the rout buffer amp. 0: off (default) 1: on log: dac ? lout/rout gain 0: 0db (default) 1: +6db addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h lineout att 0 0 0 0 atts3 atts2 atts1 atts0 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 atts3-0: analog volume control for lout/rout ( table 16) default: lmute bit = ?1?, a tts3-0 bits = ?0000? (mute) setting of atts3-0 bits is enabled at lmute bit is ?0?.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh headphone out select 1 0 0 0 0 rin2hr rin2hl lin1hr rin1hl r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 rin1hl: rin1 signal is added to the left channel of the headphone-amp 0: off (default) 1: on lin1hr: lin1 signal is added to the right channel of the headphone-amp 0: off (default) 1: on rin2hl: rin2 signal is added to the left channel of the headphone-amp 0: off (default) 1: on rin2hr: rin2 signal is added to the right channel of the headphone-amp 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh headphone att 0 hpz hmute atth4 atth 3 atth2 atth1 atth0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 atth4-0: setting of the attenuation value of output signal from headphone ( table 15) default: hmute bit = ?0?, atth4-0 bits = ?00? (0db) setting of atth4-0 bits is enabled at hmute bit is ?0?. hmute: mute control for headphone-amp 0: normal operation. atth4-0 bits control attenuation value. (default) 1: mute. atth4-0 bits are ignored. hpz: headphone-amp pull-down control 0: shorted to gnd (default) 1: pulled-down by 200k (typ)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh lineout select 0 0 0 0 rin2r rin2l lin1r rin1l r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 rin1l: rin1 signal is added to the left channel of the lineout 0: off (default) 1: on lin1r: lin1 signal is added to the right channel of the lineout 0: off (default) 1: on rin2l: rin2 signal is added to the left channel of the lineout 0: off (default) 1: on rin2r: rin2 signal is added to the right channel of the lineout 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h mono mixing 0 0 0 0 l2m l2hm l1m l1hm r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 l1hm: lin1/rin1 signal is added to headphone-amp as (l+r)/2. 0: off (default) 1: on l1m: lin1/rin1 signal is added to lout/rout as (l+r)/2. 0: off (default) 1: on l2hm: lin2/rin2 signal is added to headphone-amp as (l+r)/2. 0: off (default) 1: on l2m: lin2/rin2 signal is added to lout/rout as (l+r)/2. 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h differential select 0 0 0 0 0 0 ldifh ldif r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 ldif: switch control from in+/in ? pin to lout/rout. 0: off (default) 1: on when ldif bit = ?1?, lin1 and rin1 pins become in+ and in ? pins respectively ldifh: switch control from in+/in ? pin to headphone-amp. (setting of lidfh bit is enable at ldif bit = ?1?) 0: off (default) 1: on
asahi kasei [ak4370] ms0595-e-00 2007/03 - 46 - system design figure 38 shows the system connection diagram. an evaluation board [AKD4370] is available which demonstrates the optimum layout, power supply arrangements and measurement results. 16 220 + 220 + 16 headphone analog supply 1.6 3.6v 10 0.1 0.1 + 10 2.2 speaker spk-amp audio controller p 1000p 1 0.1 hpr hpl rin2 lin2 rin1 lin1 vss1 hvdd avdd vcom rout lout sdata bick lrck mcki dvdd vss2 mutet i2c pdn csn cclk cdti a k4370vn top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 3 4 5 6 a nalog ground digital ground + notes: - vss1 and vss2 of the ak4370 should be distributed separately from the ground of external controllers. - all digital input pins (i2c, sda/cdti, scl/cclk, cad0/csn, sdata, lrck, bick, mcki, pdn) must not be left floating. - when the ak4370 is used in master mode, lrck and bick pins are floating before the m/s bit is changed to ?1?. therefore, a 100k pull-up resistor should be connected to the lrck and bick pins of the ak4370. - when dvdd is supplied from avdd via 10 series resistor, the capacitor larger than 0.1 f should not be connected between dvdd and the ground. figure 38. typical connection diagram (in case of ac coupling to mcki)
asahi kasei [ak4370] ms0595-e-00 2007/03 - 47 - 110k 100k a k4370 lin1 pin avdd lin1hl bit hp-amp note: if the path is off and the signal is input to the input pi n, the input pin should be biased to a voltage equivalent to vcom voltage (= 0.475 x avdd) externally. figure 39. external bias circuit example for line input pin 1. grounding and power supply decoupling the ak4370 requires careful attention to power suppl y and grounding arrangements. avdd and hvdd are usually supplied from the analog power supply in the system and dvdd is supplied from avdd via a 10 resistor. alternatively if avdd and dvdd are supplied separately, avdd should be pow ered-up after dvdd rises up to 1.6v or more. when the ak4370 is powered-down, dvdd should be powered-down at the same time or later than avdd. when avdd and hvdd are supplied separately, avdd should be powered-up at the same time or earlier than hvdd. when the ak4370 is powered-down, avdd should be powered-down at the same time or later than hvdd. vss1 and vss2 must be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as close to the ak4370 as possible, with the small value ceram ic capacitors being the nearest. 2. voltage reference the input voltage to avdd sets the analog output range. usually a 0.1 f ceramic capacitor is connected between avdd and vss1. vcom is a signal ground of this chip (0.475 x avdd). the electrolytic capacitor around 2.2 f attached between vcom anvss1 eliminates the e ffects of high frequency noise, too. no load current may be drawn from vcom pin. all signals, especially clock, should be kept away from avdd and vcom in order to avoid unwanted coupling into the ak4370. 3. analog outputs the analog outputs are single-ended outputs, and 0.48 x avdd vpp(typ)@ ? 3dbfs for headphone-amp and 0.61xavdd vpp(typ) @0dbfs for lout/rout centered on th e vcom voltage. the input data format is 2?s compliment. the output voltage is a positive full s cale for 7fffffh(@24bit) and negative full scale for 800000h(@24bit). the ideal output is vcom voltage for 000000h(@24bit). dc offsets on the analog outputs is eliminated by ac coupling since the analog outputs have a dc offset equal to vcom plus a few mv.
asahi kasei [ak4370] ms0595-e-00 2007/03 - 48 - package 24pin qfn (unit: mm) 2.4 0.15 0.5 0.23 0.05 0.2 0.75 0.05 2.4 0.15 1 7 12 19 4.0 0.1 4.0 0.1 0.40 0.1 a b 0.10 m 0.08 6 24 13 18 pin #1 id (0.35 x 45 ) exposed pad note) the exposed pad on the bottom surface of the p ackage must be open or connected to the ground. package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ak4370] ms0595-e-00 2007/03 - 49 - marking 4370 x xxx 1 xxxx: date code (4 digit) revision history date (yy/mm/dd) revision reason page contents 07/03/23 00 first edition important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems c ontaining them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for us e as critical components in any safety, life support, or other hazard related device or sy stem, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aer ospace, nuclear energy, or other fiel ds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buy er or distributor of an akm produc t who distributes, disposes of, or otherwise places the product with a th ird party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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